Out-of-Band Ethernet Synchronization - FPGA Ethernet MAC

Overview

Achieving sub-microsecond synchronization over Ethernet required FPGA logic capable of processing network traffic, introducing precise timing behavior, and supporting comprehensive verification prior to hardware deployment. This project involved the development of custom PHY-adjacent HDL components, dedicated Avalon bus peripherals, and a Nios II–based control architecture to manage synchronization functions and system configuration.

Extensive simulation and verification were performed using ModelSim to validate timing relationships, protocol compliance, and system behavior before hardware integration. The resulting architecture significantly reduced hardware bring-up risk while providing a robust platform for synchronization research, experimentation, and performance evaluation.

Key Contributions:

• FPGA implementation on an Altera (Intel) Cyclone IV platform
• Development of custom Ethernet PHY-adjacent logic for synchronization and timing applications
• Comprehensive HDL verification and timing analysis using ModelSim
• Design of custom Avalon bus components and associated software drivers using SOPC Builder
• Integration of a Nios II 32-bit soft-core processor for system control, configuration, and management
• Creation of a validated FPGA and software architecture to support precise Ethernet-based synchronization experiments
• Hardware/software co-design approach enabling efficient debugging and accelerated system integration